Field of the Invention
The invention relates to a memory device, and particularly relates to a NAND flash memory device.
Description of Related Art
Along with a continuous increase of the number of transistors used in a NAND flash memory, the size of the transistors becomes smaller, and lines for connecting the transistors become denser. As a gap between word lines is reduced, a space between floating gates of unit cells is also compressed, such that the adjacent cells may interfere with each other to cause a drift of a threshold voltage (Vth), and such interference results in a fact that a distribution width of the threshold voltage is increased.
When a line width of the memory is reduced to be smaller than 2× nanometers (nm), a bit line direct interference becomes more important, especially the interference from the floating gate to an adjacent channel on a bit line direction may cause a reduction of a read window. Therefore, the excessively close threshold voltage distribution is one of the greatest challenges in current manufacturing of multi-level cells (MLC) such as triple-level cells (TLC).
For example, FIG. 1 is a layout schematic diagram of bit lines and word lines of a conventional NAND flash memory. Referring to FIG. 1, the bit lines and the word lines of the conventional NAND flash memory are configured in an orthogonal manner, for example, bit lines BL1 and BL2 are respectively orthogonal to a word line WL1. Memory cells 12 and 14 are respectively disposed at an intersection of the bit line BL1 and the word line WL1 and an intersection of the bit line BL2 and the word line WL1, and are electrically connected to the bit lines BL1 and BL2 and the word line WL1, where a parasitic coupling capacitance C1 is formed between the memory cells 12 and 14.
In detail, FIG. 2 is a layout cross-sectional view of a region 10 of FIG. 1, in which a control gate layer CG1 of the word line WL1, floating gates FG1 and FG2 corresponding to the memory cells 12 and 14, the bit lines BL1 and BL2, and an insulating layer IL1 are illustrated. Since the floating gates FG1 and FG2 are close to each other, a parasitic bit line coupling capacitance C1 is formed therebetween, and the bit line coupling capacitance C1 is a main reason that causes the bit line direct interference.